1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to the layout pattern of a DRAM (Dynamic Random Access Memory).
2. Description of the Prior Art
For a conventional DRAM having memory cells each constituted by one transistor and one capacitor, a technique of isolating a well for the formation of a memory cell from a well for the formation of a specific element as a peripheral circuit has been proposed to protect the memory cell region against noise from the peripheral circuit region. According to this technique, a so-called triple-well structure has been used. FIGS. 1 and 2 show an example of this structure, which is disclosed in Syuso Fuji et al., 1989 ISSCC DIGEST TECHNICAL PAPERS pp. 248-249 1989, February. FIG. 1 is a plan view of the structure. FIG. 2 is a sectional view taken along a line II--II in FIG. 1. A plurality of isolated P-type wells 303 are formed in an N-type substrate 301. A memory cell array 311 and an NMOS element 313 of a sense amplifier 312 are formed in each P-type well 303. In addition, a PMOS element 314 of the sense amplifier 312 and a peripheral PMOS element 315 of a power supply VCC are formed on the N-type substrate 301. P-type wells 305 and 306 are formed in the N-type substrate 301. An N-type well 307 is formed in the P-type well 306 to form a triple-well. A PMOS element 316 of a power supply VBOOT is formed in this triple-well. An NMOS element 317 as a peripheral circuit is formed in the P-type well 305. With this structure, the memory cell array 311 formed in the P-type well 303, the sense amplifier 312, and the peripheral circuit are electrically isolated from each other.
FIG. 3 is a plan view showing another structure. FIG. 4 is a sectional view taken along a line IV--IV in FIG. 3. As shown in FIGS. 3 and 4, a deep N-type well 402 is formed in a predetermined region of a P-type substrate 401, and a P-type well 403 is formed on the N-type well 402. In addition, the periphery of the P-type well 403 is surrounded by an N-type well 404 reaching the deep N-type well 402 to isolate the P-type well 403 from the P-type substrate 401. A memory cell array 411 constituting a cell array, and an NMOS element 413 of a sense amplifier 412 are formed in the P-type well 403. In addition, an N-type well 404A is formed in a portion of the P-type well 403. A PMOS element 414 of the sense amplifier 412 is formed in the N-type well 404A. An NMOS element 417 is directly formed on the portion, of the P-type substrate 401, which is located around the N-type well 404. A PMOS element 415 of a power supply VCC and a PMOS element 416 of a power supply VBOOT are respectively formed in N-type wells 405 and 406. In this structure, the memory cell array 411, the sense amplifier 412, and the peripheral circuit are isolated from each other through the N-type well 404.
Of these conventional structures, the structure shown in FIGS. 1 and 2 requires a triple-well structure to form the PMOS element 316 of the power supply VBOOT. The area of the isolation P-type well 306 is large as compared with the area of the element to be formed, thus posing a problem in realizing a high integration degree. In the structure shown in FIGS. 3 and 4, after the N-type well 404A for the formation of the PMOS element 414 of the sense amplifier 412 is formed in the P-type well 403, the N-type well 404 is formed around the N-type well 404A to isolate the P-type well 403 from the substrate 401. This structure therefore demands an extra area corresponding to the region for the formation of the N-type well 404A, in addition to the distance required between the two N-type wells 404A and 404, posing a problem in realizing a high integration degree.